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DRAM MODULE
M53233200CE0/CJ0-C
4Byte 32Mx32 SIMM
(16Mx4 base)
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DataSh
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Revision 0.0 June 1999
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DRAM MODULE
Revision History
Version 0.0 (June 1999)
* The 4th. generation of 64Mb DRAM components are applied for this module.
M53233200CE0/CJ0-C
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DRAM MODULE
M53233200CE0/CJ0-C EDO Mode 32M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V
GENERAL DESCRIPTION
The Samsung M53233200CE0/CJ0-C is a 32Mx32bits Dynamic RAM high density memory module. The Samsung M53233200CE0/CJ0-C consists of sixteen CMOS 16Mx4bits DRAMs in SOJ packages mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M53233200CE0/CJ0-C is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets.
M53233200CE0/CJ0-C
FEATURES
* Part Identification - M53233200CE0-C(4K cycles/64ms Ref, SOJ, Solder) - M53233200CJ0-C(4K cycles/64ms Ref, SOJ, Gold) * Extended Data Out Mode Operation * CAS-before-RAS & Hidden Refresh capability * RAS-only refresh capability * TTL compatible inputs and outputs * Single +5V10% power supply * JEDEC standard PDpin & pinout * PCB : Height(1420mil), double sided component
PERFORMANCE RANGE
Speed -C50 -C60
tRAC
50ns 60ns
tCAC
13ns 15ns
tRC
84ns 104ns
tHPC
20ns 25ns
PIN CONFIGURATIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 RAS3 RAS2 NC NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol NC NC Vss CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss
PIN NAMES
Pin Name A0 - A11 Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection
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.com DQ18-25, DQ27-34
W RAS0 - RAS3 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC
DQ0-7, DQ9-16
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PRESENCE DETECT PINS (Optional)
Pin PD1 PD2 PD3 PD4 50NS NC Vss Vss Vss 60NS NC Vss NC NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
M53233200CE0/CJ0-C
CAS0 RAS0
DQ1 CAS DQ2 U0 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U1 RAS DQ3 OE W A0-A11 DQ4
DQ0~DQ3
DQ1 DQ2 DQ3 DQ4 DQ1 DQ2 DQ3 DQ4
CAS RAS W A0-A11 OE
U8
CAS0 RAS1
DQ4~DQ7
CAS RAS W A0-A11 OE
U9
CAS1
DQ1 CAS DQ2 U2 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U3 RAS DQ3 OE W A0-A11 DQ4
DQ9~DQ12
DQ1 DQ2 DQ3 DQ4 DQ1 DQ2 DQ3 DQ4
CAS RAS W A0-A11 OE
U10
CAS1
DQ13~DQ16
CAS RAS A0-A11 OE W
U11
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CAS2 RAS2
DQ18~DQ21 DQ1 DQ1 CAS DQ2 DQ2 U4 .com RAS DQ3 DQ3 DQ4 OE W A0-A11 DQ4 DQ1 CAS DQ2 U5 RAS DQ3 OE W A0-A11 DQ4 DQ22~DQ25 DQ1 DQ2 DQ3 DQ4
CAS RAS W A0-A11 OE
U12
CAS2 RAS3
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CAS RAS W A0-A11 OE
U13
CAS3
DQ1 CAS DQ2 U6 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U7 RAS DQ3 OE W A0-A11 DQ4
DQ27~DQ30
DQ1 DQ2 DQ3 DQ4 DQ1 DQ2 DQ3 DQ4
CAS RAS W A0-A11 OE
U14
CAS3
DQ31~DQ34
CAS RAS W A0-A11 OE
U15
W A0-A11
Vcc 0.1 or 0.22uF Capacitor for each DRAM Vss To all DRAMs
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DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS
M53233200CE0/CJ0-C
Rating -1 to +7.0 -1 to +7.0 -55 to +125 16 50 Unit V V C W mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C)
Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC*1 0.8 Unit V V V V
*1 : VCC+2.0V at pulse width20ns, which is measured at VCC. *2 : -2.0V at pulse width20ns, whcih is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol ICC1 Speed -50 -60 Dont care -50 -60 -50 -60 Dont care -50 -60 Dont care Dont care M53233200CE0/CJ0 Min
-
Max 976 896 32 976 896 896 816 16 976 896 10 10 0.4
Unit mA mA mA mA mA mA mA mA mA mA uA uA V V
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ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL
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ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 : Hyper Page Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.
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DRAM MODULE
CAPACITANCE (TA = 25C, VCC=5V, f = 1MHz)
Item Input capacitance[A0-A11] Input capacitance[W] Input capacitance[RAS0 - RAS3] Input capacitance[CAS0 - CAS3] Input/Output capacitance[DQ0-7, 9-16,18-25, 27-34] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min
-
M53233200CE0/CJ0-C
Max 90 122 38 38 17 Unit pF pF pF pF pF
AC CHARACTERISTICS (0CTA70C, Vcc=5.0V10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time Symbol -50 Min Max Min 104 60 15 30 3 3 1 40 60 15 45 10 20 15 5 0 10 0 10 30 0 0 0 0 10 10 15 10 0 10 64 5 10 5 35 10K 45 30 10K 13 50 -60 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 3 9 9 8 8 7 4 9 3,4,10 3,4,5 3,10 3 6,12 2 Note
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CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge
84 tRC 50 tRAC 13 tCAC 25 tAA 3 tCLZ 3 13 tCEZ 1 50 tT 30 tRP 50 10K tRAS 13 tRSH 38 tCSH 8 10K tCAS .com 20 37 tRCD 15 25 tRAD 5 tCRP 0 tASR 10 tRAH 0 tASC 8 tCAH 25 tRAL 0 tRCS 0 tRCH 0 tRRH 0 tWCS 10 tWCH 10 tWP 13 tRWL 8 tCWL 0 tDS 8 tDH 64 tREF 5 tCSR 10 tCHR 5 tRPC 28 tCPA
ee DataSh
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DRAM MODULE
AC CHARACTERISTICS (0CTA70C, Vcc=5.0V10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Hyper page mode cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay W pulse width Symbol -50 Min 20 8 50 30 10 10 5 3 3 15 5 13 13 200K Max
M53233200CE0/CJ0-C
-60 Min 25 10 60 35 10 10 5 3 3 15 5 15 15 200K Max
Unit ns ns ns ns ns ns ns ns ns ns ns
Note 11
tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE
6,12 6
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles.
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2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals..com Transition 10. Operation within the tRAD(max) limit insures that tRAC(max) times are measured between VIH(min) and VIL(max) and are can be met. tRAD(max) is specified as reference point only. If assumed to be 5ns for all inputs. tRAD is greater than the specified tRAD(max) limit access time 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit and is not referenced for VOH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. is controlled by tAA. 11. tASC6ns, Assume tT=2.0ns. 12. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going.
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DRAM MODULE
READ CYCLE
M53233200CE0/CJ0-C
tRC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tCSH tRCD tRSH tCAS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH
tWEZ tAA
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tCEZ tOEZ tOEA
OE
VIH VIL -
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tOLZ tCAC tCLZ
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DQ
VOH VOL -
tRAC OPEN
tREZ
DATA-OUT
Dont care Undefined
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DRAM MODULE
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
M53233200CE0/CJ0-C
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD tRAD
tRSH tCAS
tCRP
tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL tWCS
W VIH VIL -
tWCH tWP
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OE
VIH VIL -
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tDS
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tDH
DATA-IN
DQ
VIH VIL -
Dont care Undefined
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DRAM MODULE
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
M53233200CE0/CJ0-C
tRC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tRAL tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
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OE
VIH VIL -
tOEH .com tOED tDS tDH
DATA-IN
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DQ
VIH VIL -
Dont care Undefined
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DRAM MODULE
READ - MODIFY - WRITE CYCLE
M53233200CE0/CJ0-C
tRAS
RAS VIH VIL -
tRWC
tRP
tCRP
CAS VIH VIL -
tRCD tRAD tRAH
tRSH tCAS
tASR
VIH VIL -
tASC
tCAH tCSH
A
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL -
tRWL tCWL tWP
tRWD
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OE
VIH VIL -
tOEA
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tOLZ tCLZ tCAC tAA tRAC
VALID DATA-OUT
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tOED tOEZ tDS tDH
VALID DATA-IN
DQ
VI/OH VI/OL -
Dont care Undefined
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DRAM MODULE
HYPER PAGE READ CYCLE
M53233200CE0/CJ0-C
tRASP
RAS VIH VIL o
tRP
tCSH tCRP
CAS VIH VIL -
tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS
tRCD tCAS tRAD
tASR
A VIH VIL -
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
tREZ
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRRH tRCS
W VIH VIL -
tRCH tCPA tCAC tCAC tAA tAA .com tCPA tCPA tOCH tCAC tOEA tOEA tOEP tDOH
VALID DATA-OUT
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tAA
OE VIH VIL -
tCAC tAA tCHO tOEP
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tCAC tRAC
DQ VOH VOL -
tOEA tOEZ
VALID DATA-OUT VALID DATA-OUT
tOEZ
tOEZ
tOLZ tCLZ
VALID DATA-OUT
Dont care Undefined
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DRAM MODULE
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
M53233200CE0/CJ0-C
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS
o
tHPC tCP
tRSH tCAS
tASR
A VIH VIL -
tRAH
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP tCWL
o
tWCS
tWCH tWP tCWL tRWL
tWP tCWL
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OE
VIH VIL -
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o
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tDS
DQ VIH VIL -
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
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DRAM MODULE
HYPER PAGE READ-MODIFY-WRITE CYCLE
M53233200CE0/CJ0-C
RAS
VIH VIL -
tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC
COL. ADDR
tRP
tCP tCAS tRAL tASC
COL. ADDR
tCRP
CAS
VIH VIL -
tCAH
tCAH
A
VIH VIL -
ROW ADDR
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tCPWD tOEA
tRWL tCWL tWP
tCWD tAWD tRWD tOEA tCAC tAA tRAC
OE
VIH VIL -
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tOED tDH tOEZ tDS
DataSh
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DQ
VI/OH VI/OL -
tCLZ tOLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN
tOLZ
VALID DATA-OUT
VALID DATA-IN
Dont care Undefined
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DRAM MODULE
HYPER PAGE READ AND WRITE MIXED CYCLE
M53233200CE0/CJ0-C
tRASP
RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA)
tRP
tHPC tCP
CAS VIH VIL -
tHPC tCP tCP tCAS tASC
COL. ADDR
tHPC tCAS tASC tCAH
COL. ADDR
tRAD tASR tRAH tASC
tCAS tCAH
tCAS tCAH
tCAH
tASC
COLUMN ADDRESS
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tRCS
W VIH VIL -
tRCH
tRCS
tRCH tWCS
tWCH
tRCH
tWPE
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OE VIH VIL -
.com tWED
tCPA
tCLZ
DataSh
tDH
ee
DQ
VI/OH VI/OL -
tOEA tCAC tAA tRAC
tWEZ
tWEZ
VALID
DATA-OUT
tDS
VALID DATA-IN
tAA
VALID DATA-OUT
tREZ
VALID DATA-OUT
Dont care Undefined
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DRAM MODULE
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC
RAS VIH VIL -
M53233200CE0/CJ0-C
tRP
tRAS tCRP tRPC tCRP
CAS
VIH VIL -
tASR
A VIH VIL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Dont care
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RAS VIH VIL -
tRP tRPC tCP
CAS VIH VIL -
.comtRC
tRAS
tRP
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tRPC tCSR tCHR
tWRP
W VIH VIL -
tWRH
tCEZ
DQ VOH VOL -
OPEN
Dont care Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
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DRAM MODULE
HIDDEN REFRESH CYCLE ( READ )
M53233200CE0/CJ0-C
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
CAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRRH
tWRH tWRP
tAA
OE VIH VIL -
tOEA
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tOLZ tCAC tCLZ tRAC tOEZ
DATA-OUT
tCEZ tREZ tWEZ
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DQ
VOH VOL -
OPEN
Dont care Undefined
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DRAM MODULE
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
M53233200CE0/CJ0-C
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS tCRP
tRCD
tRSH
tCHR
CAS
VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWRP tWCH tWP
tWRH
OE
VIH VIL -
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DQ VIH VIL -
tDS .com tDH
DATA-IN
ee DataSh
Dont care Undefined
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DRAM MODULE
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
M53233200CE0/CJ0-C
tRP
RAS
VIH VIL VIH VIL -
tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH
tCSR
CAS
A
VIH VIL -
COLUMN ADDRESS
READ CYCLE
W VIH VIL VIH VIL -
tWRP
tWRH
tAA tRCS tCAC
tRRH tRCH
OE
DQ
VOH VOL -
tCLZ
tOEA
tOEZ
DATA-OUT
tCEZ tREZ
tWEZ
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WRITE CYCLE
W VIH VIL VIH VIL -
tWRP
tWRH
.com tCWL
tWCS tWP
tRWL
tWCH
DataSh
ee
OE
tDS
DQ VIH VIL -
tDH
DATA-IN
READ-MODIFY-WRITE
tWRP
W VIH VIL -
tWRH
tRCS
tAWD tCWD tCAC tWP
tCWL tRWL
tAA tOEA
OE VIH VIL -
tOED tCLZ tOEZ tDS
tDH
DQ
VI/OH VI/OL VALID DATA-OUT VALID DATA-IN
Dont care Undefined
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
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DRAM MODULE
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Dont care
M53233200CE0/CJ0-C
tRP
RAS VIH VIL -
tRASS
tRPS
tRPC tCP tCSR tCHS
tRPC
CAS
VIH VIL -
tCEZ
DQ VOH VOL -
OPEN
W
VIH VIL -
tWRP
tWRH
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TEST MODE IN CYCLE
NOTE : OE , A = Dont care
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tRC tRAS tRPC tCP tCSR tCHR tRPC
DataSh
tRP
ee
tRP
RAS VIH VIL -
CAS
VIH VIL -
tWTS
W VIH VIL -
tWTH
tCEZ
DQ VOH VOL -
OPEN
Dont care Undefined
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DRAM MODULE
PACKAGE DIMENSIONS
M53233200CE0/CJ0-C
Units : Inches (millimeters)
4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051)
.400(10.16) 1.420(36.07) .250(6.35) R.062.004(R1.57.10)
.080(2.03) .250(6.35)
.250(6.35) 3.750(95.25)
( Front view )
.350(8.89) MAX
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( Back view )
.054(1.37) .047(1.19)
Gold/Solder Plating Lead
.010(.25)MAX
.100(2.54) MIN
.050(1.27)
.041.004(1.04.10)
Tolerances : .005(.13) unless otherwise specified
NOTE : The used device is 16Mx4 DRAM, SOJ DRAM Part No. : M53233200CE0/CJ0 -- K4E640411C
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DataSheet4 U .com


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